Three-level unitary interconnect structure

ABSTRACT

An interconnect structure, which can have three-levels, is formed by a metallization method in an electrical circuit. The method comprises providing a substrate assembly and depositing thereon a first dielectric layer thereover. A second dielectric layer is then deposited over the first dielectric layer. The second dielectric layer is patterned and anisotropically etched to form contact corridors. The second dielectric layer is again patterned and etched to form trenches, some of which are immediately above the contact corridors. An electrically conductive material is deposited to fill the contact corridors and trenches, and to leave a portion of the electrically conductive material above the second dielectric layer and directly above both the contact corridors and the trenches. The deposition forms a unitary three-level interconnect having a contiguous trench below a contact corridor below a metal line, where the metal line is above the second dielectric layer. An optional antireflective coating can be deposited to assist in filling the trenches and contact corridor. Finally, patterning and etching of the electrically conductive material above the second dielectric layer forms metal lines for the electrical circuit.

This application is a continuation of U.S. application Ser. No.09/565,135, filed on May 5, 2000, now U.S. Pat. No. 6,781,235, which isa divisional of U.S. application Ser. No. 08/801,819, filed on Feb. 14,1997, now U.S. Pat. No. 6,060,385, both of which are incorporated hereinby reference.

1. THE FIELD OF THE INVENTION

The present invention relates to metallization methods in themanufacture of microelectronic semiconductor devices. More particularlythe present invention relates to methods of making microelectronicsemiconductor devices having up to three-level interconnect structuresof conductive materials in which a single deposition process is used.

2. THE RELEVANT TECHNOLOGY

After fabrication of microelectronic devices in and upon semi-conductivesubstrate assemblies, metallization of the circuitry is required toplace the microelectronic devices in electrical communication one toanother according to design. Prior art designs called for contacts,trenches, and superficial wires for metallization. These designs mayrequire three or more separate depositions of conductive material inorder to complete metallization of the design. Each layer of conductivematerial was made by the steps of depositing the conductive layer,depositing and patterning a photoresist or equivalent, and etching theconductive layer.

With multiple depositions of conductive material, usually composed of ametal or a doped polysilicon, various technical challenges and devicecharacteristics arise. As semiconductor manufacturing advances from verylarge scale integration (VLSI) to ultra-large scale integration (ULSI),the devices on a semiconductor wafer shrink to sub-micron dimensions,and the circuit density increases to several million transistors perdie. In order to accomplish the required high device packing density,progressively smaller feature sizes have been required. These reducedfeature sizes include the width and spacing of interconnecting lines inthe service geometry thereof, such as corners and edges.

As features become smaller, a process flow that requires multipledepositions tends to narrow the process window for error inmisalignments. As such, a single misalignment in metallization can causea significant yield reduction.

One technical obstacle in metallization line formation is depth-of-fieldlimits in photolithography. Formation of metallization lines followscontact plug filling by deposition and patterning of a depositedmetallization material. When a contact plug is formed in a contact hole,the metallization material that fills the contact hole may have anirregular surface immediately below the contact hole due to the fillingthereof. The irregular surface of the metallization material hasdepth-of-field focusing problems due to a rough topography thereof. Therough topography can cause photolithographic steps to produce irregularmetallization line widths, which in turn lead to unpredictableresistances along the metallization lines and unreliable device speeds.

Another technical obstacle is the inherent resistance in metal-to-metalinterfaces between contacts and trenches, contacts and metallizationlines, and trenches and metallization lines. This obstacle arises whendisparate metals make up the contact and metallization line, or evenwhen metals of the same composition are poorly interfaced. The processof forming contacts in semiconductors and the subsequent wiring of thosecontacts to form a completed integrated circuit conventionally comprisestwo steps.

The first step comprises forming an aluminum or tungsten plug within acontact hole by such methods as, for example, cold or hot deposition,cold-slow, or hot-fast force filling, or metal reflow of the contacthole. There are other methods of hole filling with aluminum known in theart. Tungsten plug hole filling comprises deposition of selectedadhesional and barrier liner layers, followed by CVD of tungsten. Thecontact hole is usually defined within an insulation layer. Next, aplanarizing step leaves the titanium or tungsten plug electricallyisolated in the contact hole. The second deposition step comprisesforming a metallization line over the plug, where the metallization lineis usually composed of a material different from that of the plug.

The plug interface with the metallization line is problematic toelectrical conduction because completely connected interface areas aredifficult to achieve, particularly in dissimilar metals. Becauseresistance in electrical conduction is a function of cross-sectionalarea through the conductive body, a less than completely connectedinterface between contact or trench and metallization line causes ahigher resistance than a completely connected interface. In addition toincomplete interface connections, filling a contact hole with aluminumrequires high temperatures and pressures that may cause large orirregular grain structures to grow. Large or irregular grain structuresresist flow and etchback, and do not conduct current as well asfine-grained structures.

Still other technical obstacles are electromigration and metal creep.These involve the transport of metal atoms along the direction ofelectron flow in the conductive lines, and can lead to failure of theconductive lines. These obstacles are discussed below in turn.

Aluminum-copper electromigration is well established in a structure withan aluminum-copper metallization line interfacing with a titanium ortungsten plug. The phenomenon occurs because copper diffusivity throughtitanium or tungsten is much lower than copper diffusivity throughaluminum. Therefore, the copper is depleted from the area of thetitanium or tungsten plug by the current flow, leading to failure at theinterface between the titanium or tungsten plug and the aluminum-copperline.

Metal creep, on the other hand, occurs due to differences in the thermalcoefficients of expansion between metals, insulators, and siliconmaterials. Differences in thermal coefficients of expansion can build upstresses in the metal interconnects, which can lead to migration ofatoms from one area to another. This migration of atoms forms voids orvacancies in the metal interconnect which can cause an electricalfailure.

The problems of cumulative misalignments and of electrical resistance atmetal-metal interfaces with its several destructive effects are to beavoided. What is needed is methods of making multi-level interconnectstructures that overcome these problems.

SUMMARY OF THE INVENTION

The present invention comprises a method of forming a three-levelinterconnect metallization scheme for placing microelectronic devices ina circuit in electrical communication. The inventive method comprisesforming a substrate assembly and depositing thereon a first dielectriclayer. As used herein, a substrate assembly is one or more layers orstructures upon a substrate. A second dielectric layer is then depositedover the first dielectric layer. The second dielectric layer is thenpatterned and etched twice. The first pattern and etch of the seconddielectric layer is an anisotropic etch that forms contact corridors. Byway of example, and not by way of limitation, a contact corridor can bea via. The second pattern and etch of the second dielectric layer formsone or more trenches. Preferably, one or more of the trenches will beformed directly above and contiguous to a corresponding contactcorridor.

After trench formation, a filling step is performed. During the fillingstep, an electrically conductive material is deposited into the contactcorridors and into the trenches so as to leave excess electricallyconductive material above the contact corridors and trenches and uponthe second dielectric layer. Additional steps, as a part of the fillingstep, may be taken to ensure a complete filling of the contact corridorsand trenches. The excess electrically conductive material is situateddirectly above the contact corridors and trenches, thus forming aunitary integrated three-level interconnect.

After the single deposition step, but before the filling step, anoptional antireflective coating is deposited to assist in a completefilling of the contact corridors and trenches. An optional planarizationof the electrically conductive material can be carried out after thefilling step.

After the filling step, either with or without the optionalplanarization of the electrically conductive material, a second optionalantireflective coating is deposited to assist in reducing reflectionsthat hinder subsequent photolithographic processing.

Finally, patterning and etching of the excess electrically conductivematerial is done. The remaining electrically conductive material in thecontact corridors, the trenches, and above the second dielectric layeris formed into a single integral structure, the material of which issupplied to the substrate assembly in a single deposition step. Theelectrically conductive material in forming single integral structuresin combinations of the contact corridors, trenches, and portions abovethe second dielectric layer each have a substantially constantelectrical resistance from the top surface thereof to the bottom surfacethereof. The substantially constant electrical resistance is due to theabsence of metal-to-metal interfaces therein, which absence is inherentto the single deposition of the electrically conductive material.

These and other features of the present invention will become more fullyapparent from the following description and appended claims, or may belearned by the practice of the invention as set forth hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to illustrate the manner in which the above-recited and otheradvantages of the invention are obtained, a more particular descriptionof the invention briefly described above will be rendered by referenceto specific embodiments thereof which are illustrated in the appendeddrawings. Understanding that these drawings depict only typicalembodiments of the invention and are not therefore to be consideredlimiting of its scope, the invention will be described and explainedwith additional specificity and detail through the use of theaccompanying drawings in which:

FIG. 1 is a cross-sectional view of a semiconductor device on asubstrate assembly during fabrication in which typical structures havebeen fabricated within and upon a semiconductor substrate assembly.

FIG. 2 is a cross-sectional view of the semiconductor device as seen inFIG. 1 and illustrates contact hole fabrication.

FIG. 3 is a cross-sectional view of the semiconductor device as seen inFIG. 2 and illustrates trench formation in an upper dielectric layer ofthe semiconductor device.

FIG. 4 is a cross-sectional view of the semiconductor device as seen inFIG. 3 and illustrates formation of a metallization layer.

FIG. 5 is a cross-sectional view of the semiconductor device as seen inFIG. 4 and illustrates the metallization thereof, wherein circuitryhaving several interconnect features has been completed with a singledeposition and, patterning of a conductive material.

FIG. 6 illustrates a plan view of the semiconductor device of FIG. 5 inwhich wiring, trenches, and contacts are depicted.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to methods of making integratedthree-level interconnect structures, two level interconnect structures,and one-level contacts in an integrated circuit, each said method usinga single deposition of a conductive material for metallization of theintegrated circuit.

FIG. 1 illustrates a semiconductor device 10. Semiconductor device 10comprises, by way of non-limiting example, a substrate assembly 12 withactive areas (not shown), oxide regions 14, gate structures 16, a firstdielectric layer 18, and a second dielectric layer 20. Other structures,although not illustrated in FIG. 1, could also be a part ofsemiconductor device 10, including stacked or trench capacitors, as wellas other structures.

The inventive method comprises depositing first dielectric layer 18 asshown in FIG. 1. To prevent silicon contamination, first dielectriclayer 18 can optionally be composed of a material known to be a siliconimpurity getterer such as a doped glass or the like.

If needed, first dielectric layer 18 can be planarized following thedeposition thereof. Planarization techniques include chemical-mechanicalplanarization (CMP), mechanical planarization (MP), dry etchback, otherisotropic etching, reflow, and the like depending upon the nature offirst dielectric layer 18. The purpose of such a planarizing step is toprovide a relatively flat surface upon which second dielectric layer 20will be formed. First and second dielectric layers 18, 20 willpreferably have different compositions so as to allow the patterning ofsecond dielectric layer 20 with selective etching of first dielectriclayer 18, as is described below.

Planarization, although often a necessary step, may be omitted foreither or both the first and the second dielectric layers after thedeposition thereof. Omission of a planarizing step is possible where thetopography of substrate assembly 12 so permits, or where as-depositedfirst and/or dielectric layers 18, 20 are sufficiently fluid so as tonot require a planarization step.

After the deposition and optional planarizing of first dielectric layer18, second dielectric layer 20 is deposited and may also be optionallyplanarized if needs be. Deposition of second dielectric layer 20 can bea deposition process that includes silicon dioxide formed by tetraethylortho silicate (TEOS), nitride, boron-phosphorus silicate glass (BPSG),and the like according to the specific application.

Second dielectric layer 20 is then patterned with a first mask 24 andanisotropically etched to form contact corridors 21 which extend throughfirst and second dielectric layers, 18, 20. Contact corridors 21 areillustrated in FIG. 2. Depending upon the application, contact corridors21 can be used to expose an active area (not shown) of substrateassembly 12, the top of gate structure 16, and regions between thebottom of contact corridors 21 and substrate assembly 12.

Following the formation of contact corridors 21, trenches 30 are formed.To form trenches 30, a second mask 26 is used to pattern seconddielectric layer 20. Second mask 26 is designed to situate one or moretrenches 30 above one or more contact corridors 21, and to situate oneor more trenches 30 above first dielectric layer

FIG. 3 illustrates the result of an etch with the pattern from secondmask 26, which result includes both trenches 30 and contact corridors21.

In forming trenches 30, the etch recipe used in the etch step can beselective to first dielectric layer 18 and substantially unselective tosecond dielectric layer 20. Alternatively, it may be desirable toprovide a etch recipe that etches first dielectric layer 18 faster so asto reshape contact corridors 21, if so desired. As such, applicationsare contemplated in which the second etch step has an etch recipe thatis partially selective to first dielectric layer 18 and less selectiveto second dielectric layer 20. As such, trenches 30 are formed, whilecontact corridors 21 are changed as to the dimensions from the firstetch step described above.

After trenches 30 are formed, first and second masks 24, 26 arestripped, and an electrically conductive material 40 is deposited asshown in FIG. 4. Electrically conductive material 40 can be composed ofdoped polysilicon, aluminum and aluminum alloys of AlCu, AlSi, AlSiCu,AlTi, their combinations, and equivalents. Other aluminum alloys thatare contemplated as consistent with the present invention comprise AlAg,AlAu, AlMn, AlGe, AlW, AlCuGe, AlNi, their combinations, andequivalents.

After initial deposition of electrically conductive material 40, anoptional antireflective coating 32, illustrated in FIG. 4, is deposited.Antireflective coating 32 is useful as an etching assistant forsubsequent patterning and etching of electrically-conductive material 40to form metal lines therefrom. The antireflective quality ofantireflective coating 32 benefits subsequent photolithographic steps inpatterning electrically conductive material 40 by reducing imagescattering or blurring inherent in U the reflective nature ofelectrically conductive material 40. Antireflective coating 32 is alsouseful as an energy-absorbing layer which maintains an elevatedtemperature of electrically conductive material 40 while the same fillsvoids within trenches 30 and contact corridors 21. Examples ofantireflective coatings include organic layers, SiN and equivalents.

Electrically conductive material 40 is deposited within trenches 30 andcontact corridors 21 by known deposition methods such as physical vapordeposition (PVD), hot PVD, high density plasma physical vapor deposition(HDPPVD), and chemical vapor deposition (CVD). Complete filling oftrenches 30 and of contact corridors 21 may be accomplished by suchadditional processing, where necessary or desired, as reflow, highpressure fill, their combinations, and the like. As seen in FIG. 4,electrically conductive material 40 has two regions which are generallyindicated as an embedded metallization region 22 and a superficialmetallization region 23. Embedded metallization region 22 is defined asa portion of electrically-conductive material 40 below an upper surfaceof second dielectric layer 20. As seen in FIG. 4, embedded metallizationregion 22 is depicted as being below a line A-A. As such, embeddedmetallization region 22 is that portion of electrically conductivematerial 40 that fills trenches 30 and contact corridors 21. Superficialmetallization region 23 is defined as that portion of electricallyconductive material 40 above the upper surface of second dielectriclayer 20. As seen in FIG. 4, superficial metallization region 23 isdepicted as being above the line A-A.

Following the deposition of electrically conductive material 40, andoptionally filling steps described above, electrically conductivematerial 40 may then be planarized so as to form a planar surface uponsuperficial metallization region 23. This optional planarization aidssubsequent photolithography processing of electrically conductivematerial 40 incident to the patterning thereof which is necessary foretching metal lines therefrom. As described above, it is desirable topattern a planar surface so as to prevent the formation of metal linesof varying widths due to improper photolithography. This optionalplanarization can be followed by a second optional antireflectivecoating deposition, resulting in a substantially planar layer similar toantireflective coating 32 seen in FIG. 4, which assists as describedabove in improving the accuracy of patterning second dielectric layer 20during photolithography processing.

Second dielectric layer 20 is patterned with a third mask 28, as seen inillustrated in FIG. 4. An etch of second dielectric layer 20 throughthird mask 28 forms metal lines having a shape and orientation accordingto a design for an electrical circuit metallization scheme. Atrench-contact structure 25 is formed as an integral combination withincontact corridor 21 and trench 30. A wire-trench structure 27 is formedas an integral combination of superficial metallization region 23 andcontact corridor 21. A wire-trench-contact structure 29, seen in FIG. 6,is formed as an integral combination of superficial metallization region23, trench 30, and contact corridor 21. A wire-contact structure 31 isformed as an integral combination of superficial metallization region 23and contact corridor 21. Finally, a trench structure 33 is illustratedwhere a portion of superficial metallization region 23 seen in FIG. 4was removed to result in trench structure 33 seen in FIG. 5. As such,FIG. 5 illustrates the result of the inventive method in which fourinterconnect structures are depicted.

Although semiconductor device 10 is depicted in FIG. 5 ascross-sectional, it is also illustrative to understand the method andstructures of the present invention by viewing semiconductor device 10from the plan view of FIG. 6. In FIG. 6, which is taken along a lineB--B within second dielectric layer 20 of FIG. 5, trench-contactstructure 25, wire-trench structure 27, wire-trench-contact structure29, wire-contact structure 31, and trench 33 are illustrated.

As stated above, “metal-to-metal interfaces” are problematic inelectrical circuits due to inherent resistance increases therein.Metal-to-metal interfaces are known in multiple depositions required formetallization of circuits having contacts or vias, trenches, andsuperficial wiring. This metallization includes such structures as busbars, cables, bonding pads and the like. The inventive method, however,accomplishes metallization of an electrical circuit in a singledeposition step. As such, the problem known to multiple levelinterconnects as “metal-to-metal interfaces” is substantiallyeliminated. The inventive method also accomplishes a three levelsmetallization without intervening metal-to-metal interfaces. Thesubstantial elimination of metal-to-metal interfaces in metallizationalso reduces a tendency for metal migration in that there is an absenceof inadequately connected interfacial areas that cause highertemperatures and metal migration. The specific resistance, defined asthe resistance per a given cross-sectional area, is substantiallyuniform throughout single and multiple level interconnect structures.

The present invention may be embodied in other specific forms withoutdeparting from its spirit or essential characteristics. The describedembodiments are to be considered in all respects only as illustrativeand not restrictive. The scope of the invention is, therefore, indicatedby the appended claims and their combination in whole or in part ratherthan by the foregoing description. All changes that come within themeaning and range of equivalency of the claims are to be embraced withintheir scope.

1. An article of manufacture comprising: a first dielectric layer upon asubstrate assembly, said first dielectric layer defining a first contactcorridor having a first maximum width; a second dielectric layer uponsaid first dielectric layer and having an upper surface, said seconddielectric layer defining a first trench having a second maximum widthsubstantially not less than the first maximum width; and a first metallayer extending from a top surface above the second dielectric layerthrough said first trench and terminating at a bottom surface thereofwithin said first contact corridor, said metal layer substantiallyfilling said first trench and said first contact corridor, said firstmetal layer having a first portion thereof extending from the firsttrench and above the second dielectric layer with a third maximum widthsubstantially not less than the second maximum width, said first metallayer having a substantially constant electrical resistance from the topsurface thereof to the bottom surface thereof within said first contactcorridor.
 2. An article of manufacture as defined in claim 1, whereinthe first metal layer is a unitary structure free of metal-to-metalinterfaces between the top surface thereof and the bottom surfacethereof.
 3. An article of manufacture as defined in claim 1, whereinsaid first dielectric layer is substantially composed of a material thatis dissimilar from a material from which said second dielectric layer issubstantially composed.
 4. An article of manufacture as defined in claim1, further comprising a gate structure situated on said substrateassembly, wherein said first contact corridor terminates at a gatesurface upon said gate structure, said bottom surface of said firstmetal layer being in contact with said gate surface.
 5. An article ofmanufacture as defined in claim 1, wherein the bottom surface of saidfirst metal layer is situated upon said substrate assembly.
 6. Anarticle of manufacture as defined in claim 1, further comprising: asecond contact corridor defined by said first dielectric layer having afirst maximum width; a second trench defined by said second dielectriclayer and having a second maximum width substantially not less than thefirst maximum width; and a second metal layer extending from a topsurface substantially not above the second dielectric layer, throughsaid second trench, and terminating at a bottom surface thereof withinsaid second contact corridor, said second metal layer substantiallyfilling said second trench and said second contact corridor, said secondmetal layer having a substantially constant electrical resistance fromthe top surface thereof to the bottom surface thereof within said secondcontact corridor.
 7. An article of manufacture as defined in claim 6,wherein the bottom surface of each said first and second metal layers issituated upon said substrate assembly.
 8. An article of manufacture asdefined in claim 6, wherein said first and second metal layers aresubstantially composed of a material selected from the group consistingof doped polysilicon, W, aluminum alloys, AlCu, AlSi, AlSiCu, AlTi,AlAg, AlAu, AlMn, AlGe, AIW, AlCuGe, AlNi, and their combinations.
 9. Anarticle of manufacture as defined in claim 6, further comprising: athird trench defined by said second dielectric layer and having a secondmaximum width; and a third metal layer extending from a top surfacesubstantially not above the second dielectric layer, through said thirdtrench, and terminating at a bottom surface thereof upon a top surfaceof said first dielectric layer, said third metal layer substantiallyfilling said third trench, said third metal layer having a substantiallyconstant electrical resistance from the top surface thereof to thebottom surface thereof upon said first dielectric layer.
 10. Aninterconnect structure comprising: a first dielectric layer upon asubstrate assembly; a second dielectric layer upon said first dielectriclayer and having a planarized top surface thereon; a first recessextending through said second dielectric layer and into said firstdielectric layer; a second recess extending through said first recessand into said second dielectric layer, said second recess having a firsttrench defined by said second dielectric layer and a first contactcorridor defined by said first dielectric layer, said first contactcorridor having a first maximum width, said first trench having a secondmaximum width not less than the first maximum width; and a first metallayer that is upon said planar top surface of said second dielectriclayer, said first metal layer filling said first contact corridor andsaid first trench, said first metal layer extending from a top surfaceabove the second dielectric layer through said first trench andterminating at a bottom surface thereof within said first contactcorridor, said first metal layer having a first portion thereofextending from the first trench and above the second dielectric layerwith a third maximum width not less than the second maximum width. 11.The interconnect structure as defined in claim 10, wherein said firstmetal layer has a constant electrical resistance from the top surfacethereof to the bottom surface thereof.
 12. An interconnect structurecomprising: a first dielectric layer upon a substrate assembly; a seconddielectric layer upon said first dielectric layer; a first recessextending through said second dielectric layer and into said firstdielectric layer; a second recess extending through said first recessand into said second dielectric layer, said second recess having a firsttrench defined by said second dielectric layer and a first contactcorridor defined by said first dielectric layer, said first contactcorridor having a first maximum width, said first trench having a secondmaximum width not less than the first maximum width; and a first metallayer that: fills both the first contact corridor and the first trench;extends from a top surface above the second dielectric layer throughsaid first trench and terminates at a bottom surface thereof within thefirst contact corridor; and has a first portion that extends from thefirst trench and above the second dielectric layer with a third maximumwidth not less than the second maximum width, wherein the firstdielectric layer is composed of a material that is dissimilar from amaterial from which said second dielectric layer is composed.
 13. Theinterconnect structure as defined in claim 12, wherein the top surfaceon the first portion of the first metal layer is planarized and hasthereon an antireflective coating.
 14. The interconnect structure asdefined in claim 12, wherein said first metal layer is composed of amaterial selected from the group consisting of doped polysilicon, W,aluminum alloys, AlCu, AlSi, AlSiCu, AlTi, AlAg, AlAu, AlMn, AlGe, AlW,AlCuGe, AlNi, and their combinations.
 15. The interconnect structure asdefined in claim 12, wherein said first metal layer has a constantelectrical resistance from the top surface thereof to the bottom surfacethereof.
 16. The interconnect structure as defined in claim 12, wherein:a top surface of the first dielectric layer is planar; and the seconddielectric layer is formed upon the planar top surface of the firstdielectric layer.
 17. The interconnect structure as defined in claim 12,wherein: a top surface of the second dielectric layer is planar; and thefirst metal layer is upon the planar top surface of the seconddielectric layer.
 18. The interconnect structure as defined in claim 12,wherein said first dielectric layer is formed upon a silicon surface ofsaid substrate assembly, said first dielectric layer being composed of amaterial having a silicon impurity getterer property.
 19. Theinterconnect structure as defined in claim 12, wherein the first metallayer is a unitary structure free of metal-to-metal interfaces betweenthe top surface thereof and the bottom surface thereof.
 20. Theinterconnect structure as defined in claim 12, wherein: the substrateassembly comprises a gate structure; the first contact corridorterminates at a gate surface upon said gate structure; and the bottomsurface of the first metal layer is in contact with said gate surface.21. The interconnect structure as defined in claim 12, wherein thebottom surface of said first metal layer is situated upon said substrateassembly.
 22. The interconnect structure as defined in claim 12, furthercomprising: a third recess extending through said first dielectric layerand into said second dielectric layer; a fourth recess extending throughsaid second recess and into said second dielectric layer, said fourthrecess having a second trench defined by said second dielectric layerand a second contact corridor defined by said first dielectric layer,said second contact corridor having a first maximum width, said secondtrench having a second maximum width not less than the first maximumwidth; and a second metal layer that: fills the second contact corridorand said second trench; extends from a top surface not above the seconddielectric layer, through said second trench, and terminates at a bottomsurface thereof within said second contact corridor; and has a constantelectrical resistance from the top surface thereof to the bottom surfacethereof.
 23. The interconnect structure as defined in claim 22, whereinthe bottom surface of each said first and second metal layers issituated upon said substrate assembly.
 24. The interconnect structure asdefined in claim 22, wherein said first and second metal layers arecomposed of a material selected from the group consisting of dopedpolysilicon, W, aluminum alloys, AlCu, AlSi, AlSiCu, AlTi, AlAg, AlAu,AlMn, AlGe, AIW, AlCuGe, AlNi, and their combinations.
 25. Theinterconnect structure as defined in claim 22, further comprising: athird trench defined by said second dielectric layer and having a secondmaximum width extending through said second dielectric layer andterminating upon a top surface of said first dielectric layer; and athird metal layer that: extends from a top surface thereof not above thesecond dielectric layer, through said third trench, and terminates at abottom surface thereof upon said top surface of said first dielectriclayer; fills the third trench; and has a constant electrical resistancefrom the top surface thereof to the bottom surface thereof.